The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device.
In the integrated circuit field of electronics industry, there is a growing demand for further high integration and further speed-up. The progress in integration has enlarged the scale of circuits, leading to an increase in difficulty level in circuit design.
An integrated circuit obtained by mounting both a logic circuit and a memory circuit on the same semiconductor substrate is called “mixed circuit”. The mixed circuit has an improved integration degree, because the logic circuit and the memory circuit are arranged with a short distance. In addition, it has an improved operation rate because a wiring distance between circuits can be decreased.
Patent Documents 1 to 3 describe a semiconductor device having a mixed circuit. This semiconductor device has, on one substrate, a logic portion and a DRAM (Dynamic Random Access Memory) portion. The logic portion has, on the substrate, a first transistor, a first contact, a wiring, and an interlayer insulating layer. The first contact electrically couples the first transistor and the wiring. This wiring is buried in the interlayer insulating layer. The DRAM portion has, on the substrate, a second transistor, a second contact, a capacitor, and an interlayer insulating layer. The second contact electrically couples the second transistor and the capacitor. The capacitor is buried in a recess (which may hereinafter be called “capacitor burying recess) formed in the interlayer insulating layer. The capacitor and the wiring are formed in the same layer. The interlayer insulating layer in which the capacitor burying recess has been formed is made of the same material as that of the interlayer insulating layer in which the wiring has been buried.    [Patent Document 1] Japanese Patent Laid-Open No. 2007-201101    [Patent Document 2] Japanese Patent Laid-Open No. 2000-332216    [Patent Document 3] Japanese Patent Laid-Open No. 2004-342787